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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICR_ICFGR0, Interrupt Configuration Register 0</h1><p>The GICR_ICFGR0 characteristics are:</p><h2>Purpose</h2>
        <p>Determines whether the corresponding SGI is edge-triggered or level-sensitive.</p>
      <h2>Configuration</h2>
        <p>A copy of this register is provided for each Redistributor.</p>
      <h2>Attributes</h2>
        <p>GICR_ICFGR0 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config15</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config14</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config13</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config12</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config11</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config10</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config9</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config8</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config7</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config6</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config5</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config4</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config3</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config2</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config1</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">Int_config0</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">Int_config&lt;x&gt;, bits [2x+1:2x], for x = 15 to 0</h4><div class="field">
      <p>Indicates whether the is level-sensitive or edge-triggered.</p>
    <table class="valuetable"><tr><th>Int_config&lt;x&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Corresponding interrupt is level-sensitive.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Corresponding interrupt is edge-triggered.</p>
        </td></tr></table><p>SGIs are always edge-triggered.</p>
<p>When the interrupt is visible to the current Security state, a read of this bit always returns the correct value to indicate the interrupt triggering method.</p><p>The reset behavior of this field is:</p><ul><li>On a GIC reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing GICR_ICFGR0</h2>
        <p>This register is used when affinity routing is enabled.</p>

      
        <p>When affinity routing is disabled for the Security state of an interrupt, the field for that interrupt is <span class="arm-defined-word">RES0</span> and an implementation is permitted to make the field RAZ/WI in this case. Equivalent functionality is provided by GICD_ICFGR&lt;n&gt; with n=0.</p>

      
        <p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses.</p>
      <h4>GICR_ICFGR0 can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Redistributor</td><td>SGI_base</td><td><span class="hexnumber">0x0C00</span></td><td>GICR_ICFGR0</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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